1. Field of the Invention
The present invention relates to a solid-state image pickup device and a method of manufacturing the same.
2. Description of the Related Art
With recent increase in degree of integration of semiconductor elements, solid-state image pickup devices have also been increased in the number of pixels and advanced in miniaturization.
On the other hand, characteristic degradation attendant thereon is becoming a great problem.
For example, an SN ratio is important for the improvement of image quality. Specifically, as the miniaturization progresses, a decrease of photons that can be taken in due to the miniaturization of a photodiode (PD) as a photoelectric conversion element inevitably reduces a signal quantity. It is thus necessary to improve the SN ratio by reducing noise.
In CMOS (Complementary Metal Oxide Semiconductor) image sensors, in particular, as shown in FIG. 14, a charge obtained by photoelectric conversion in a photodiode 221 is accumulated in a floating diffusion 226 via a transfer transistor 222 and thereafter subjected to signal amplification in an amplifying transistor 224 in many cases.
A noise proportional to a frequency generated in the amplifying transistor 224, or 1/f noise, is dominant as random noise of a pixel, and it is important to suppress the noise. In general, the following relation holds for the 1/f noise.in2=KF((IdAF)/(CoxWLefffEF))  (1)
where in2 is drain current noise density [A2/Hz], KF (flicker noise coefficient) is a factor dependent on the element, Id is a drain current, Cox is a gate capacitance per unit area, and Leff is an effective gate length.
This is disclosed in IEEE Transaction on Electron Devices, Vol. 48, No. 5, May 2001, pp. 921 to 927.
According to the above Equation (1), a reduction of line width of the amplifying transistor 224, that is, miniaturization of the amplifying transistor 224 sharply increases the noise. KF is a factor dependent on the amplifying transistor 224, and is greatly affected by process factors.
One of the process factors is a stress applied to a channel part of the amplifying transistor 224. For higher speed and lower power consumption of a minute pixel, reducing gate wiring resistance and contact resistance by applying silicide to transistors within a pixel region is a very effective means, and the amplifying transistor 224 is no exception.
Generally, silicide techniques have been introduced to a generation of 0.25 μm or later in CMOS logic.
While a pixel region in a CMOS image sensor is highly likely to operate as a device as long as ohmic characteristics are maintained, techniques for reducing resistance such as salicide formation or the like become necessary with a reduction of a contact diameter.
However, a local tensile stress occurs in a channel part of a fine amplifying transistor where salicide is formed.
In addition, a correlation is found between stress and 1/f noise. The application of tensile stress increases the 1/f noise regardless of whether a carrier species is electrons or holes, or in both cases of an N-MOS and a P-MOS (see Authored by T. Ohguro, Y. Okayama, K. Matsuzawa, K. Matsunaga, N. Aoki, K. Kojima, H. S. Momose, and K. Ishimaru, The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11 CMOS″ 2003 Symposium on VLSI Technology Digest of Technical Papers, 2003, p. 37 and Authored by Shigenobu Maeda, You-Seung Jin, Jung-A Choi, Sun-Young Oh, Hyun-Woo Lee, Jae-Yoon Yoo, Min-Chul Sun, Ja-Hum Ku, Kwon Lee, Su-Gon Bae, Sung-Gun Kang, Jeong-Hwan Yang, Young-Wug Kim, and Kwang-Pyuk Suh, “Impact of Mechanical Stress Engineering on Flicker Noise Characteristics” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 102 to 103, for example).
For the above-described reasons, when pixels are miniaturized and salicide is introduced into the pixels, it is difficult to tolerate noise degradation when a high SN ratio is to be achieved.
A process of manufacturing a CMOS image sensor in related art will next be described with reference to FIGS. 15A to 15E.
As shown in FIG. 15A, a P-type well region 212 is formed in an N-type silicon substrate 211.
Next, a photodiode 221 for performing photoelectric conversion is formed at a predetermined position on the surface side of the silicon substrate 211. The photodiode 221 is formed by a P-type region, an N-type region, and a P-type region from a bottom layer by performing ion implantation of phosphorus (P) as an N-type impurity and boron (B) as a P-type impurity using an ion implantation mask formed by patterning a resist film formed on the silicon substrate 211.
The energy of the ion implantation is adjusted such that the photodiode 221 is desirably formed between the surface of the semiconductor substrate 211 and a depth of 5 μm to 15 μm for visible light, and is for example formed between the surface of the semiconductor substrate 211 and a depth of about 5 μm.
As described above, an N-type substrate is used as the silicon substrate 211, and therefore isolation of the photodiode 221 is performed by the P-type well region 212.
Next, MOS type transistors within a pixel are formed.
As shown in FIG. 15B, a gate insulating film 231 is formed on the silicon substrate 211, and then a polysilicon film for forming gate electrodes is formed. Next, a resist mask (not shown) to serve as an etching mask for forming the gate electrodes is formed on the polysilicon film. With the resist mask used as etching mask, the polysilicon film is patterned, whereby the gate electrodes 232 of a transfer transistor, a reset transistor, an amplifying transistor, and a selecting transistor are formed by polysilicon.
Next, as shown in FIG. 15C, side walls 233 are formed on the side part of each of the gate electrodes 232 for a purpose of suppressing a short channel effect of a MOS transistor (not shown) of a peripheral circuit, the reset transistor, the amplifying transistor, the selecting transistor, and the like. The side walls 233 are formed by a silicon oxide film, for example. However, the side walls 233 can be formed by a silicon nitride film.
Next, a resist mask (not shown) is formed, and diffusion layers 234, 235, 236, and 237 serving as sources and drains of the transistors are formed in the semiconductor substrate 211 by ion implantation using the resist mask.
In general, when holes and electrons are compared with each other as carriers, holes are more easily trapped on the gate insulating film 231 and the interface. Thus, this time, electrons are selected as carriers, that is, N-MOS is formed. A floating diffusion 226 is also formed at the same time by the ion implantation.
Next, as shown in FIG. 15D, silicide layers 241 to 249 are formed on the diffusion layers 234 to 237, on the floating diffusion 226, and on the gate electrodes 232, respectively, by a salicide process.
Prior to the salicide process, because silicide layers have low optical transparency, a silicide blocking film 251 is formed on the photodiode 221 to prevent the formation of a silicide layer on the photodiode 221. The silicide blocking film 251 is desirably formed by a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like. A titanium silicide, a tantalum silicide, a molybdenum silicide, a nickel silicide, a tungsten silicide, a nickel-platinum silicide or the like can be applied as the silicide layers 241 to 249.
Next, as shown in FIG. 15E, an etching stopper film 252 for temporarily stopping etching at a time of contact processing is formed on an entire surface over the silicon substrate 211. The etching stopper film 252 is formed by a silicon nitride film, a silicon oxynitride film or the like that makes it easy to secure a selective etching ratio with respect to a silicon oxide film as an interlayer insulating film to be formed later.
Thereafter, though not shown, an interlayer insulating film is formed, and a contact part is formed using tungsten.
Further, a wiring layer, an interlayer insulating film, a planarizing insulating film, a color filter layer, and a microchip lens, and the like are formed, whereby the CMOS image sensor is completed.
However, in the above-described CMOS image sensor, variations in 1/f noise increase significantly due not only to a finer design rule of the amplifying transistor (AMP) but also to the load of tensile stress on the channel part by the silicide layers 243 and 244 of the amplifying transistor 224. As a result, the SN ratio is lowered, and it is difficult to obtain sufficient image quality.